The present invention relates to a method for deleting unused (unnecesssary) logic gates, and more particularly, relates to the technology effective for use in a method for deleting unused gates when converting, for example, total logic circuit diagrams in board image designed using a plurality of standard logic integrated circuits (ICs) into total logic circuit diagrams for a single-chip semiconductor integrated circuit device such as a gate array and a master-slice IC. Further, the present invention relates to a method for manufacturing a master-slice semiconductor circuit device using the aforesaid method for deleting unused gates.
Because of their improved versatility, standard logic ICs, such as standard TTL (transistor-transistor logic) ICs and standard CMOS (complementary metal-oxide-semiconductor) ICs are widely used for designing various logic boards. Meanwhile, semiconductor manufactures have numbers of hitherto designed logic circuit diagrams in board image on hand. With the advancement of the semiconductor manufacturing technology in recent years, it has become possible to form total logic circuits designed in board image on one chip.
On the other hand, since versatility of each standard logic IC has been enhanced as described above, there are a number of unused logic circuits included in a logic circuit actually designed in board image. For example, it is often the case that only 6-bit portions of an 8-bit register of a TTL IC are used. In such a case, logic circuits constituting 2-bit portions of the register become unused gates.
Therefore, when it is intended to reform existing or newly designed total logic circuits in a TTL board image into a single-chip semiconductor integrated circuit such as a gate array or a master-slice IC, it is desired to obtain total logic circuits for providing the semiconductor integrated circuit from which unused gates as described above are deleted. This is because enlargement of the chip area and increase in cost can be prevented by such arrangement.
A method for deleting unused basic cells is disclosed in U.S. Pat. No. 4,602,339 issued to Aihara, et al. The method for deleting unused basic cells is such that (1) determine the basic cells whose output terminals are not connected to any element to be unused basic cells and delete them and (2) also deletes basic cells whose output terminals have come out of connection with any element as a result of the process (1) described above.
Sugisaki et al. made a report on cell reduction function on Nov. 1, 1985, in "Electronic Technology", Vol 27, No. 12 (1985-11), pp. 45-49, published by the Nikkan Kogyo Shimbun, Ltd. The cell reduction function, here, includes backward reduction whereby such gates which are in the paths for functional blocks whose input/output terminals are open are automatically deleted and forward reduction whereby such gates which are in the paths for those whose input terminals are logically fixed are simplified.
Further, Toida et al. made a report on TTL-GA (Gate Array) automatic conversion program, entitled "CMOS 1.0 .mu.m gate array `HG62E Series`", in "Hitachi Review", Vol. 69, No. 7 (1987-07), pp. 79-82.
The present inventors found that the known method for deleting unused gates has the following problem.
The problem will be described taking as an example a synchronous divide-by-16 counter having 5-bit output and using standard TTL (Type LS161) as shown by broken line in FIG. 4. When this divide-by-16 counter is used as a divide-by-8 counter having 3-bit output, an output Q.sub.D and a ripple carrier output terminal CO come to be unused. Therefore, when using the known method for deleting unused gates, the AND gate G5 connected with ripple carrier output terminals CO can be deleted and the inverter N4 whose output terminal becomes unused as the result of the deletion of the AND gate circuit G5 can be deleted.
On the other hand, since the output signal of the flip-flop circuit FF1 coupled with the output terminal Q.sub.D is used as an input to the AND gate circuit G6, the flip-flop circuit which should be deleted is left undeleted. As the result, gate circuits G6, G7, G8, G9, and G10 and inverter N5 which should be deleted are also left undeleted. Therefore, there has been a problem with the known unused gate deleting method that, when there is an unused gate having such a feedback loop, the gate cannot be deleted.
In brief, the determination whether or not a gate is an unused gate is dependent on whether or not the output of the gate is unused. Therefore, even if a gate should be deleted, the gate is not deleted if its output is considered to be in use. As the result, a gate array comes to be formed based on logic circuits including unnecessary logic gates, which results in enlarged size and increased cost of the gate array.